This invention relates to the sharing of an adaptive dispersion compensation engine (ADCE) among a plurality of high-speed serial interface channels, especially in a programmable logic device.
Programmable logic devices (PLDs) frequently incorporate high-speed serial interfaces to accommodate high-speed (i.e., greater than 1 Gbps) serial I/O standards. Typically, a PLD may have multiple high-speed serial interface channels. In use, different ones of such channels may have different characteristics, particularly if the user configures them for different standards, but also because of the length of the serial link involved and transmission conditions between the interface and the remote device. With multiple such channels all having different characteristics, the user is faced with the need to provide different amounts of equalization to compensate for attenuation. The amount of equalization of any particular setting in any particular channel may vary with backplane length, backplane type (e.g., backplane material), backplane aging, process conditions at the time of PLD manufacture, data rate, voltage, temperature, etc.
Manually determining the optimal settings for each link would be extremely time-consuming. There may be large numbers (e.g., hundreds or thousands) of permutations of various programmable settings in each channel. Moreover, selection of the appropriate combination of settings frequently is done by trial-and-error.
The STRATIX® II GX PLD, available from Altera Corporation, of San Jose, Calif., includes an integrated ADCE. The integrated ADCE automatically performs the trial-and-error examination of the output of the equalizer stages and adjusts the equalizer settings to increase or decrease the amount of equalization. This examination is performed in real time, adjusting to the changing environment and the aging process. In the STRATIX® II GX PLD, each transceiver channel is equipped with an ADCE. However, the ADCE adds significantly to the area occupied by each channel. The largest STRATIX® II GX device has twenty channels. Thus, the provision of an ADCE in each channel adds significantly to device size. In addition, because ADCEs are complex and therefore subject to fabrication difficulties, a large number of ADCEs on the PLD reduces yield.
Therefore, it would be desirable to be able to reduce the number of ADCEs on a PLD.